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    » A new test pattern generation method for delay fault testing
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    ET
    2002
    67views more  ET 2002»
    On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
    13 years 8 months ago
    On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
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    In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our te...
    Emmanouil Kalligeros, Xrysovalantis Kavousianos, D...
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    SAC
    2006
    ACM
    155views Applied Computing» more  SAC 2006»
    A new method of generating synchronizable test sequences that detect output-shifting faults based on multiple UIO sequences
    13 years 8 months ago
    A new method of generating synchronizable test sequences that detect output-shifting faults based on multiple UIO sequences
    Download  www.cs.northwestern.edu
    The objective of testing is to determine the conformance between a system and its specification. When testing distributed systems, the existence of multiple testers brings out the...
    Kai Chen, Fan Jiang, Chuan-dong Huang
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    ET
    2006
    154views more  ET 2006»
    An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults
    13 years 8 months ago
    An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults
    Download  www.eng.auburn.edu
    We present an efficient built-in self-test (BIST) architecture for testing and diagnosing stuck-at faults, delay faults, and bridging faults in FPGA interconnect resources. The BIS...
    Jack Smith, Tian Xia, Charles E. Stroud
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    DFT
    2002
    IEEE
    127views VLSI» more  DFT 2002»
    A New Functional Fault Model for FPGA Application-Oriented Testing
    14 years 1 months ago
    A New Functional Fault Model for FPGA Application-Oriented Testing
    Download  www.cercom.polito.it
    1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...
    Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo ...
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    ATS
    2005
    IEEE
    132views Hardware» more  ATS 2005»
    Concurrent Test Generation
    14 years 2 months ago
    Concurrent Test Generation
    Download  www.eng.auburn.edu
    We define a new type of test, called “concurrent test,” for a combinational circuit. Given a set of target faults, a concurrent-test is an input vector that detects all (or m...
    Vishwani D. Agrawal, Alok S. Doshi
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