Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
Patrick Girard, Christian Landrault, Serge Pravoss...
Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation. This paper improves concurrent BIST techniques based on a deterministic test ...
Michael A. Kochte, Christian G. Zoellin, Hans-Joac...
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
The paper presents a test pattern generation and fault simulation methodology for the detection of catastrophic faults in analogue circuits. The test methodology chosen for evalua...
Stephen J. Spinks, Chris D. Chalk, Ian M. Bell, Ma...