179 search results - page 9 / 36 » A new test pattern generation method for delay fault testing |
MEMOCODE
2007
IEEE
14 years 3 months ago
2007
IEEE
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
IOLTS
2000
IEEE
14 years 1 months ago
2000
IEEE
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
ETS
2009
IEEE
13 years 6 months ago
2009
IEEE
Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation. This paper improves concurrent BIST techniques based on a deterministic test ...
ITC
1995
IEEE
14 years 7 days ago
1995
IEEE
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
DFT
1997
IEEE
14 years 28 days ago
1997
IEEE
The paper presents a test pattern generation and fault simulation methodology for the detection of catastrophic faults in analogue circuits. The test methodology chosen for evalua...