Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead

Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation. This paper improves concurrent BIST techniques based on a deterministic test set. Here, the test patterns are specially generated with a small number of specified bits. This results in very low test latency, which reduces the likelihood of fault accumulation. Experiments with a large number of circuits show that the hardware overhead is significantly lower than the overhead for previously published methods. Furthermore, the method allows to tradeoff fault coverage, test latency and hardware overhead.

• Type: Journal
• Year: 2009
• Where: ETS
• Authors: Michael A. Kochte, Christian G. Zoellin, Hans-Joachim Wunderlich
• Keywords: Concurrent Bist Techniques, ETS 2009, Hardware, Low Test Latency, Test Latency