Sciweavers

405 search results - page 18 / 81
» A novel cache architecture with enhanced performance and sec...
Sort
View
IEEEPACT
2009
IEEE
14 years 2 months ago
SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors
Abstract—This paper proposes a new software-oriented approach for managing the distributed shared L2 caches of a chip multiprocessor (CMP) for latency-oriented multithreaded appl...
Lei Jin, Sangyeun Cho
CODES
2010
IEEE
13 years 5 months ago
Dynamic, non-linear cache architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for generalpurpos...
Garo Bournoutian, Alex Orailoglu
TC
2010
13 years 5 months ago
PERFECTORY: A Fault-Tolerant Directory Memory Architecture
—The number of CPUs in chip multiprocessors is growing at the Moore’s Law rate, due to continued technology advances. However, new technologies pose serious reliability challen...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
ICS
1999
Tsinghua U.
13 years 11 months ago
Performance impact of proxies in data intensive client-server applications
Large client-server data intensive applications can place high demands on system and network resources. This is especially true when the connection between the client and server s...
Michael D. Beynon, Alan Sussman, Joel H. Saltz
ICOIN
2005
Springer
14 years 1 months ago
The Content-Aware Caching for Cooperative Transcoding Proxies
The Web is rapidly increasing its reach beyond the desktop to various devices and the transcoding proxy is appeared to support web services efficiently. Recently, the cooperative t...
Byoung-Jip Kim, Kyungbaek Kim, Daeyeon Park