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MICRO
2006
IEEE
132views Hardware» more  MICRO 2006»
14 years 2 months ago
Scalable Cache Miss Handling for High Memory-Level Parallelism
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
James Tuck, Luis Ceze, Josep Torrellas
SIMULATION
2010
178views more  SIMULATION 2010»
13 years 3 months ago
Application-level Simulation for Network Security
We introduce and describe a novel network simulation tool called NeSSi (Network Security Simulator). NeSSi incorporates a variety of features relevant to network security distingu...
Stephan Schmidt, Rainer Bye, Joël Chinnow, Ka...
IACR
2011
128views more  IACR 2011»
12 years 8 months ago
Identity-Based Cryptography for Cloud Security
—Cloud computing is a style of computing in which dynamically scalable and commonly virtualized resources are provided as a service over the Internet. This paper, first presents ...
Hongwei Li, Yuanshun Dai, Bo Yang
CODES
2006
IEEE
13 years 10 months ago
Architectural support for safe software execution on embedded processors
The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and mo...
Divya Arora, Anand Raghunathan, Srivaths Ravi, Nir...
OOPSLA
2009
Springer
14 years 3 months ago
A concurrent dynamic analysis framework for multicore hardware
Software has spent the bounty of Moore’s law by solving harder problems and exploiting abstractions, such as highlevel languages, virtual machine technology, binary rewritdynami...
Jungwoo Ha, Matthew Arnold, Stephen M. Blackburn, ...