405 search results - page 70 / 81 » A novel cache architecture with enhanced performance and sec... |
IEEEPACT
2008
IEEE
14 years 1 months ago
2008
IEEE
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
ICC
2007
IEEE
14 years 1 months ago
2007
IEEE
— The EPC Network is an industry proposal to build a global information architecture for objects carrying RFID tags with Electronic Product Codes (EPC). A so-called Object Naming...
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
Networks-on-Chip (NoCs) become a critical design factor as chip multiprocessors (CMPs) and systems on a chip (SoCs) scale up with technology. With fundamental benefits of high ban...
ICS
2007
Tsinghua U.
14 years 1 months ago
2007
Tsinghua U.
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
This paper describes a novel engine, called PE-ICE (Parallelized Encryption and Integrity Checking Engine), enabling to guarantee confidentiality and integrity of data exchanged b...