405 search results - page 76 / 81 » A novel cache architecture with enhanced performance and sec... |
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
HPCA
2004
IEEE
14 years 7 months ago
2004
IEEE
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...
SIGCOMM
2009
ACM
14 years 2 months ago
2009
ACM
The threat of commoditization poses a real challenge for service providers. While the end-to-end principle is often paraphrased as “dumb network, smart end-systems”, the origi...
MMNS
2007
13 years 9 months ago
2007
Recent growth of the multimedia content delivery over the Internet and the popularity of the peer-to-peer (P2P) architecture have opened new horizons for emerging novel services ov...
WWW
2003
ACM
14 years 8 months ago
2003
ACM
A computationally enhanced message contains some embedded programmatic components that are interpreted and executed automatically upon receipt. Unlike ordinary text email or insta...