252 search results - page 16 / 51 » A novel high throughput reconfigurable FPGA architecture |
AHS
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
TVLSI
2008
13 years 7 months ago
2008
This paper describes a reconfigurable architecture based on field-programmable gate-array (FPGA) technology for monitoring and analyzing network traffic at increasingly high networ...
FPGA
2004
ACM
14 years 29 days ago
2004
ACM
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
Network Intrusion Detection and Prevention Systems have emerged as one of the most effective ways of providing security to those connected to the network, and at the heart of alm...
ARC
2009
Springer
14 years 7 days ago
2009
Springer
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...