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» A novel high throughput reconfigurable FPGA architecture
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FCCM
2009
IEEE
115views VLSI» more  FCCM 2009»
14 years 19 days ago
Multi-Core Architecture on FPGA for Large Dictionary String Matching
FPGA has long been considered an attractive platform for high performance implementations of string matching. However, as the size of pattern dictionaries continues to grow, such ...
Qingbo Wang, Viktor K. Prasanna
ISCAS
2005
IEEE
153views Hardware» more  ISCAS 2005»
14 years 2 months ago
A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher
—A high-throughput hardware architecture and FPGA implementation of the 64-bit NESSIE proposal, MISTY1 block cipher, is presented in this paper. This architecture, in contrast to...
Paris Kitsos, Michalis D. Galanis, Odysseas G. Kou...
DATE
2005
IEEE
180views Hardware» more  DATE 2005»
14 years 2 months ago
A Coprocessor for Accelerating Visual Information Processing
Visual information processing will play an increasingly important role in future electronics systems. In many applications, e.g. video surveillance cameras, data throughput of mic...
Walter Stechele, L. Alvado Cárcel, Stephan ...
FPL
1998
Springer
106views Hardware» more  FPL 1998»
14 years 1 months ago
Acceleration of Satisfiability Algorithms by Reconfigurable Hardware
Abstract. We present different architectures to solve Boolean satisfiability problems in instance-specific hardware. A simulation of these architectures shows that for examples fro...
Marco Platzner, Giovanni De Micheli
RTSS
2006
IEEE
14 years 2 months ago
MCGREP - A Predictable Architecture for Embedded Real-Time Systems
Real-time systems design involves many important choices, including that of the processor. The fastest processors achieve performance by utilizing architectural features that make...
Jack Whitham, Neil C. Audsley