252 search results - page 20 / 51 » A novel high throughput reconfigurable FPGA architecture |
ERSA
2006
13 years 10 months ago
2006
In this paper we first outline and discuss the issues of currently accepted computational models for hybrid CPU/FPGA systems. Then, we discuss the need for researchers to develop ...
ERSA
2006
13 years 10 months ago
2006
In this case study, various ways to partition a code between the microprocessor and FPGA are examined. Discrete image convolution operation with separable kernel is used as the ca...
TRETS
2010
13 years 7 months ago
2010
s, and abstractions, typically enabling faster development times than with traditional Hardware ion Languages (HDLs). However, programming at a higher level of abstraction is typic...
ISCAS
2005
IEEE
14 years 2 months ago
2005
IEEE
—Unknown protein sequences are often compared to a set of known sequences (a database scan) to detect functional similarities. Even though efficient dynamic programming algorithm...
DSD
2009
IEEE
14 years 19 days ago
2009
IEEE
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computat...