252 search results - page 21 / 51 » A novel high throughput reconfigurable FPGA architecture |
SIPS
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract— In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization effi...
ERSA
2009
13 years 6 months ago
2009
Many scientific and engineering applications, which are increasingly being ported from software to reconfigurable platforms, require Gaussian-distributed random numbers. Thus, the...
ISCAS
1994
IEEE
14 years 27 days ago
1994
IEEE
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
In this paper, a real output queuing switch prototype implementation is presented. This implementation is based on a novel high speed multidrop backplane and a general purpose lin...
APCCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
— We propose a VLSI architecture for the single-chip realization of 2D spatio-temporal IIR digital filters, consisting of a meshed connection of concurrent identical vector-proce...