252 search results - page 28 / 51 » A novel high throughput reconfigurable FPGA architecture |
DATE
2008
IEEE
2008
IEEE
An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications
14 years 3 months ago
Novel reconfigurable computing platforms enable efficient realizations of complex signal processing applications by allowing exploitation of parallelization resulting in high thro...
JSA
2010
13 years 3 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
INTEGRATION
2008
13 years 7 months ago
2008
This paper presents a Viterbi Decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has b...
FPGA
2009
ACM
14 years 1 months ago
2009
ACM
This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed archit...
CASES
2008
ACM
13 years 10 months ago
2008
ACM
The Field Programmable Compressor Tree (FPCT) is a programmable compressor tree (e.g., a Wallace or Dadda Tree) intended for integration in an FPGA or other reconfigurable device....