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» A novel high throughput reconfigurable FPGA architecture
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FPL
2008
Springer
116views Hardware» more  FPL 2008»
13 years 10 months ago
NOC architecture design for multi-cluster chips
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
Henrique C. Freitas, Philippe Olivier Alexandre Na...
FPGA
2006
ACM
90views FPGA» more  FPGA 2006»
14 years 14 days ago
Improving performance and robustness of domain-specific CPLDs
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurabil...
Mark Holland, Scott Hauck
AHS
2007
IEEE
251views Hardware» more  AHS 2007»
14 years 24 days ago
System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...
Ali Ahmadinia, Balal Ahmad, Tughrul Arslan
VLSID
2006
IEEE
128views VLSI» more  VLSID 2006»
14 years 9 months ago
Custom Reconfigurable Architecture for Autonomous Fault-Recovery of MEMS Vibratory Sensor Electronics
This paper presents a novel custom-reconfigurable architecture, which is tailored to accomplish the electronic circuits associated with MEMS vibratory sensors. The paradigm of thi...
Evangelos F. Stefatos, Tughrul Arslan, Didier Keym...
ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
14 years 2 months ago
A high performance distributed-parallel-processor architecture for 3D IIR digital filters
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
Arjuna Madanayake, Leonard T. Bruton