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» A novel improvement technique for high-level test synthesis
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CODES
2006
IEEE
14 years 1 months ago
Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability
Reliability in embedded processors can be improved by control flow checking and such checking can be conducted using software or hardware. Proposed software-only approaches suffe...
Roshan G. Ragel, Sri Parameswaran
SRDS
2010
IEEE
13 years 5 months ago
Fault-Tolerant Aggregation for Dynamic Networks
Data aggregation is a fundamental building block of modern distributed systems. Averaging based approaches, commonly designated gossip-based, are an important class of aggregation ...
Paulo Jesus, Carlos Baquero, Paulo Sérgio A...
DAC
2006
ACM
14 years 8 months ago
Timing-based delay test for screening small delay defects
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
ICML
2007
IEEE
14 years 8 months ago
Asymptotic Bayesian generalization error when training and test distributions are different
In supervised learning, we commonly assume that training and test data are sampled from the same distribution. However, this assumption can be violated in practice and then standa...
Keisuke Yamazaki, Klaus-Robert Müller, Masash...
ISQED
2009
IEEE
112views Hardware» more  ISQED 2009»
14 years 2 months ago
Estimation and optimization of reliability of noisy digital circuits
— With continued scaling, reliability is emerging as a critical challenge for the designers of digital circuits. The challenge stems in part from the lack of computationally efï¬...
Satish Sivaswamy, Kia Bazargan, Marc D. Riedel