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ISCAS
2002
IEEE
111views Hardware» more  ISCAS 2002»
14 years 2 months ago
CASCADE - configurable and scalable DSP environment
As the complexity of embedded systems grows rapidly, it is common to accelerate critical tasks with hardware. Designers usually use off-the-shelf components or licensed IP cores t...
Tay-Jyi Lin, Chein-Wei Jen
ISVLSI
2002
IEEE
104views VLSI» more  ISVLSI 2002»
14 years 2 months ago
Scalable VLSI Architecture for GF(p) Montgomery Modular Inverse Computation
Modular inverse computation is needed in several public key cryptographic applications. In this work, we present two VLSI hardware implementations used in the calculation of Montg...
Adnan Abdul-Aziz Gutub, Alexandre F. Tenca, &Ccedi...
ITC
2002
IEEE
114views Hardware» more  ITC 2002»
14 years 2 months ago
Scan Power Reduction Through Test Data Transition Frequency Analysis
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
KR
2010
Springer
14 years 1 months ago
Decomposing Description Logic Ontologies
Recent years have seen the advent of large and complex ontologies, most notably in the medical domain. As a consequence, structuring mechanisms for ontologies are nowadays viewed ...
Boris Konev, Carsten Lutz, Denis Ponomaryov, Frank...
ESA
2009
Springer
109views Algorithms» more  ESA 2009»
14 years 1 months ago
Preemptive Online Scheduling with Reordering
We consider online preemptive scheduling of jobs, arriving one by one, on m identical parallel machines. A buffer of a fixed size K > 0, which assists in partial reordering of...
György Dósa, Leah Epstein
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