134 search results - page 6 / 27 » A performance optimization method by gate sizing using stati... |
ACL
2004
13 years 9 months ago
2004
This paper introduces an indexing method based on static analysis of grammar rules and type signatures for typed feature structure grammars (TFSGs). The static analysis tries to p...
PATMOS
2005
Springer
14 years 1 months ago
2005
Springer
This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to max...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Ignoring the effect of simultaneous switching for logic gates causes silicon failures for high performance microprocessor designs. The main reason to omit this effect is the run...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
In the nanometer manufacturing region, process variation causes significant uncertainty for circuit performance verification. Statistical static timing analysis (SSTA) is thus dev...
ICCAD
2003
IEEE
14 years 28 days ago
2003
IEEE
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...