Sciweavers

420 search results - page 23 / 84
» A pseudo-hierarchical methodology for high performance micro...
Sort
View
VLSID
1999
IEEE
97views VLSI» more  VLSID 1999»
14 years 27 days ago
A New Methodology for Concurrent Technology Development and Cell Library Optimization
To minimize the time to market and cost of new sub 0.25um process technologies and products, PDF Solutions, Inc., has developed a new comprehensive approach based on the use of pr...
Marko P. Chew, Sharad Saxena, Thomas F. Cobourn, P...
VTS
1999
IEEE
66views Hardware» more  VTS 1999»
14 years 27 days ago
A New Bare Die Test Methodology
1 While multichip module technology has been developed for high performance IC applications, the technology is not widely adopted due to economical reasons. One of the reasons that...
Zao Yang, K.-T. Cheng, K. L. Tai
MICRO
2006
IEEE
127views Hardware» more  MICRO 2006»
14 years 2 months ago
A Predictive Performance Model for Superscalar Processors
Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed si...
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthav...
HPCN
1997
Springer
14 years 23 days ago
High Performance Simulation for Resonant-Mass Gravitational Radiation Antennas
Abstract. In this paper the design and validation of a high performance simulation is discussed that is of critical value to the feasibility study of the GRAIL project, the aim of ...
Jan F. de Ronde, G. Dick van Albada, Peter M. A. S...
ICCAD
2003
IEEE
135views Hardware» more  ICCAD 2003»
14 years 1 months ago
ATPG for Noise-Induced Switch Failures in Domino Logic
Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with te...
Rahul Kundu, R. D. (Shawn) Blanton