420 search results - page 44 / 84 » A pseudo-hierarchical methodology for high performance micro... |
ASPLOS
2004
ACM
14 years 2 months ago
2004
ACM
Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010. This paper proposes an efficient error detection techniqu...
IUI
2012
ACM
12 years 4 months ago
2012
ACM
One Feature (1F) is a simple and intuitive pruning strategy that reduces considerably the amount of computations required by Nearest-Neighbor gesture classifiers while still pres...
VLSID
2010
IEEE
14 years 17 days ago
2010
IEEE
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
CLUSTER
2006
IEEE
14 years 2 months ago
2006
IEEE
The effect of the operating system on application performance is an increasingly important consideration in high performance computing. OS kernel measurement is key to understandi...
ASAP
2010
IEEE
13 years 10 months ago
2010
IEEE
In a traditional Network-on-Chip (NoC), latency and power dissipation increase with system size due to its inherent multi-hop communications. The performance of NoC communication ...