420 search results - page 47 / 84 » A pseudo-hierarchical methodology for high performance micro... |
CVPR
2007
IEEE
14 years 10 months ago
2007
IEEE
Measuring system performance seems conceptually straightforward. However, the interpretation of the results and predicting future performance remain as exceptional challenges in s...
MTV
2007
IEEE
14 years 3 months ago
2007
IEEE
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
This paper advances a new methodology based on signal-path information to resolve the problem of device-level placement for analog layout. This methodology is mainly based on three...
MICRO
1994
IEEE
14 years 24 days ago
1994
IEEE
High performance architectures have always had to deal with the performance-limiting impact of branch operations. Microprocessor designs are going to have to deal with this proble...
ICCD
2007
IEEE
14 years 16 days ago
2007
IEEE
Prior work has shown that collapsible pipelining techniques have the potential to significantly reduce clocking activity, which can consume up to 70% of the dynamic power in moder...