420 search results - page 50 / 84 » A pseudo-hierarchical methodology for high performance micro... |
DAC
2000
ACM
14 years 9 months ago
2000
ACM
Substrate noise caused by large digital circuits will degrade the performance of analog circuits located on the same substrate. To simulate this performance degradation, the total...
FPGA
2003
ACM
14 years 1 months ago
2003
ACM
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...
INFOCOM
2009
IEEE
14 years 3 months ago
2009
IEEE
Abstract—Detecting the occurrence and location of performance anomalies (e.g., high jitter or loss events) is critical to ensuring the effective operation of network infrastructu...
CASES
2003
ACM
14 years 1 months ago
2003
ACM
In an embedded system, the cost of storing a program onchip can be as high as the cost of a microprocessor. Compressing an application’s code to reduce the amount of memory requ...
ISCA
2002
IEEE
14 years 1 months ago
2002
IEEE
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...