420 search results - page 54 / 84 » A pseudo-hierarchical methodology for high performance micro... |
DDECS
2009
IEEE
14 years 3 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
CF
2004
ACM
14 years 2 months ago
2004
ACM
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
SC
2009
ACM
14 years 3 months ago
2009
ACM
Reconfigurable computing (RC) systems based on FPGAs are becoming an increasingly attractive solution to building parallel systems of the future. Applications targeting such syste...
ASAP
2010
IEEE
13 years 9 months ago
2010
IEEE
Abstract—The demand for biomedical implants keeps increasing. However, most of the current implant design methodologies involve custom-ASIC design. The SiMS project aims to chang...
ISSRE
2008
IEEE
14 years 3 months ago
2008
IEEE
Systems connected to the Internet are highly susceptible to denial-of-service attacks that can compromise service availability, causing damage to customers and providers. Due to e...