3 search results - page 1 / 1 » A rescheduling and fast pipeline VLSI architecture for lifti... |
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper, we propose a fast pipeline VLSI architecture for 1D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predict...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
In this paper, an efficient VLSI architecture for a fast computation of the 2-D discrete wavelet transform (DWT) is proposed. The architecture employing a three-stage cascade in p...
DATE
1998
IEEE
14 years 24 days ago
1998
IEEE
This paper presents a VLSI Architecture to implement the forward and inverse 2-D Discrete Wavelet Transform (FDWT/IDWT), to compress medical images for storage and retrieval. Loss...