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» A routing algorithm for flip-chip design
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GECCO
2006
Springer
164views Optimization» more  GECCO 2006»
14 years 19 days ago
Biobjective evolutionary and heuristic algorithms for intersection of geometric graphs
Wire routing in a VLSI chip often requires minimization of wire-length as well as the number of intersections among multiple nets. Such an optimization problem is computationally ...
Rajeev Kumar, Pramod Kumar Singh, Bhargab B. Bhatt...
IPTPS
2003
Springer
14 years 2 months ago
Rationality and Self-Interest in Peer to Peer Networks
Much of the existing work in peer to peer networking assumes that users will follow prescribed protocols without deviation. This assumption ignores the user’s ability to modify ...
Jeffrey Shneidman, David C. Parkes
SIGCOMM
2010
ACM
13 years 9 months ago
Achieving O(1) IP lookup on GPU-based software routers
IP address lookup is a challenging problem due to the increasing routing table size, and higher line rate. This paper investigates a new way to build an efficient IP lookup scheme...
Jin Zhao, Xinya Zhang, Xin Wang, Xiangyang Xue
DAC
2012
ACM
11 years 11 months ago
Exploiting die-to-die thermal coupling in 3D IC placement
In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce t...
Krit Athikulwongse, Mohit Pathak, Sung Kyu Lim
DAC
2008
ACM
14 years 10 months ago
Enhancing timing-driven FPGA placement for pipelined netlists
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
Kenneth Eguro, Scott Hauck