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» A routing algorithm for flip-chip design
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CASES
2004
ACM
13 years 11 months ago
Automatic data partitioning for the agere payload plus network processor
With the ever-increasing pervasiveness of the Internet and its stringent performance requirements, network system designers have begun utilizing specialized chips to increase the ...
Steve Carr, Philip H. Sweany
SIMUTOOLS
2008
13 years 9 months ago
Simulating SMEPP middleware
Embedded Peer-to-Peer Systems (EP2P) represent a new challenge in the development of software for distributed systems. The main objective of the SMEPP (Secure Middleware for Embed...
Javier Barbarán, Carlos Bonilla, Jose &Aacu...
DAC
2003
ACM
14 years 8 months ago
On-chip logic minimization
While Boolean logic minimization is typically used in logic synthesis, logic minimization can be useful in numerous other applications. However, many of those applications, such a...
Roman L. Lysecky, Frank Vahid
MOBICOM
2009
ACM
14 years 2 months ago
A scalable micro wireless interconnect structure for CMPs
This paper describes an unconventional way to apply wireless networking in emerging technologies. It makes the case for using a two-tier hybrid wireless/wired architecture to inte...
Suk-Bok Lee, Sai-Wang Tam, Ioannis Pefkianakis, So...
MOBICOM
2006
ACM
14 years 1 months ago
Double rulings for information brokerage in sensor networks
We study the problem of information brokerage in sensor networks, where information consumers (sinks, users) search for data acquired by information producers (sources). Innetwork...
Rik Sarkar, Xianjin Zhu, Jie Gao