1017 search results - page 65 / 204 » A routing algorithm for flip-chip design |
COMSWARE
2007
IEEE
14 years 3 months ago
2007
IEEE
: In this paper, we investigate the problem of routing lightpaths on an arbitrary physical topology following a Design Protection approach, such that virtual topology remains conne...
ASPDAC
2005
ACM
13 years 11 months ago
2005
ACM
Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...
ISPD
2005
ACM
14 years 2 months ago
2005
ACM
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
SOCC
2008
IEEE
14 years 3 months ago
2008
IEEE
Abstract— In this paper we present an efficient system-onchip implementation of a 1-Gbps LDPC decoder for 4G (or beyond 3G) wireless standards. The decoder has a scalable datapa...
DAC
2003
ACM
14 years 2 months ago
2003
ACM
In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement...