Sciweavers

34 search results - page 4 / 7
» A sample-based cache mapping scheme
Sort
View
ICCD
2004
IEEE
125views Hardware» more  ICCD 2004»
14 years 4 months ago
IPC Driven Dynamic Associative Cache Architecture for Low Energy
Existing schemes for cache energy optimization incorporate a limited degree of dynamic associativity: either direct mapped or full available associativity (say 4-way). In this pap...
Sriram Nadathur, Akhilesh Tyagi
EGH
2007
Springer
14 years 1 months ago
Accelerating real-time shading with reverse reprojection caching
Evaluating pixel shaders consumes a growing share of the computational budget for real-time applications. However, the significant temporal coherence in visible surface regions, ...
Diego F. Nehab, Pedro V. Sander, Jason Lawrence, N...
TOG
2002
153views more  TOG 2002»
13 years 7 months ago
Interactive global illumination in dynamic scenes
In this paper, we present a system for interactive computation of global illumination in dynamic scenes. Our system uses a novel scheme for caching the results of a high quality p...
Parag Tole, Fabio Pellacini, Bruce Walter, Donald ...
DATE
2009
IEEE
127views Hardware» more  DATE 2009»
14 years 2 months ago
Process variation aware thread mapping for Chip Multiprocessors
Abstract—With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiproce...
Shengyan Hong, Sri Hari Krishna Narayanan, Mahmut ...
APCSAC
2003
IEEE
14 years 23 days ago
Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor
The StrongARM processor features virtually-addressed caches and a TLB without address-space tags. A naive implementation therefore requires flushing of all CPU caches and the TLB ...
Adam Wiggins, Harvey Tuch, Volkmar Uhlig, Gernot H...