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» A scalable virtual circuit routing scheme for ATM networks
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FPL
2005
Springer
112views Hardware» more  FPL 2005»
14 years 28 days ago
Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement
Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate ...
Anthony J. Yu, Guy G. Lemieux
SIGMETRICS
1997
ACM
153views Hardware» more  SIGMETRICS 1997»
13 years 11 months ago
Queue Management for Explicit Rate Based Congestion Control
Rate based congestion control has been considered desirable, both to deal with the high bandwidth-delay products of today's high speed networks, and to match the needs of eme...
Qingming Ma, K. K. Ramakrishnan
WS
2006
ACM
14 years 1 months ago
Modeling Ad-hoc rushing attack in a negligibility-based security framework
In this paper, we propose a formal notion of network security for ad hoc networks. We adopt a probabilistic security framework, that is, security is defined by a polynomially bou...
Jiejun Kong, Xiaoyan Hong, Mario Gerla
CODES
2005
IEEE
14 years 1 months ago
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs
To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of...
Anthony Leroy, Paul Marchal, Adelina Shickova, Fra...
EUROPAR
2005
Springer
14 years 28 days ago
Cost / Performance Trade-Offs and Fairness Evaluation of Queue Mapping Policies
Whereas the established interconnection networks (ICTN) achieve low latency by operating in the linear region, i.e. oversizing the fabric, the recent strict cost and power constrai...
Teresa Nachiondo Frinós, Jose Flich, Jos&ea...