Sciweavers

359 search results - page 20 / 72
» A section cache system designed for VLIW architectures
Sort
View
DSN
2006
IEEE
14 years 1 months ago
Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures
—Multithreaded servers with cache-coherent shared memory are the dominant type of machines used to run critical network services and database management systems. To achieve the h...
Albert Meixner, Daniel J. Sorin
PG
2007
IEEE
14 years 1 months ago
The Mental Canvas: A Tool for Conceptual Architectural Design and Analysis
We describe a computer graphics system that supports conceptual architectural design and analysis. We use as a starting point the traditional sketchbook drawings that architects u...
Julie Dorsey, Songhua Xu, Gabe Smedresman, Holly E...
COMCOM
2002
120views more  COMCOM 2002»
13 years 7 months ago
An interactive video delivery and caching system using video summarization
With the advance of high-speed network technologies, the availability and popularity of streaming media content over the Internet has grown rapidly in recent years. The delivery a...
Sung-Ju Lee, Wei-Ying Ma, Bo Shen
MICRO
2010
IEEE
159views Hardware» more  MICRO 2010»
13 years 5 months ago
Fractal Coherence: Scalably Verifiable Cache Coherence
We propose an architectural design methodology for designing formally verifiable cache coherence protocols, called Fractal Coherence. Properly designed to be fractal in behavior, t...
Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin
DAC
2008
ACM
14 years 8 months ago
Miss reduction in embedded processors through dynamic, power-friendly cache design
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
Garo Bournoutian, Alex Orailoglu