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» A section cache system designed for VLIW architectures
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ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
13 years 12 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
DAC
2005
ACM
13 years 9 months ago
Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility
In this paper we present the impact of dynamically translating any sequence of instructions into combinational logic. The proposed approach combines a reconfigurable architecture ...
Antonio Carlos Schneider Beck, Luigi Carro
FPL
2000
Springer
128views Hardware» more  FPL 2000»
13 years 11 months ago
Verification of Dynamically Reconfigurable Logic
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
David Robinson, Patrick Lysaght
C5
2004
IEEE
13 years 11 months ago
Design for an Extensible Croquet-Based Framework to Deliver a Persistent, Unified, Massively Multi-User, and Self-Organizing Vir
We describe a design for a collaborative Virtual Learning Environment (VLE) to support massively multi-user and multi-institutional learning communities. This architecture extends...
Mark P. McCahill, Julian Lombardi
CONEXT
2007
ACM
13 years 11 months ago
On the cost of caching locator/ID mappings
Very recent activities in the IETF and in the Routing Research Group (RRG) of the IRTG focus on defining a new Internet architecture, in order to solve scalability issues related ...
Luigi Iannone, Olivier Bonaventure