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» A section cache system designed for VLIW architectures
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IJES
2007
79views more  IJES 2007»
13 years 7 months ago
Energy-aware compilation and hardware design for VLIW embedded systems
Abstract: Tomorrow’s embedded devices need to run high-resolution multimedia applications which need an enormous computational complexity with a very low energy consumption const...
José L. Ayala, Marisa López-Vallejo,...
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
13 years 12 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
MICRO
1994
IEEE
96views Hardware» more  MICRO 1994»
13 years 11 months ago
A fill-unit approach to multiple instruction issue
Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility...
Manoj Franklin, Mark Smotherman
ISVLSI
2006
IEEE
150views VLSI» more  ISVLSI 2006»
14 years 1 months ago
Design and Analysis of a Low Power VLIW DSP Core
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
Chan-Hao Chang, Diana Marculescu
CASES
2001
ACM
13 years 11 months ago
Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures
In this paper we describe a design exploration methodology for clustered VLIW architectures. The central idea of this work is a set of three techniques aimed at reducing the cost ...
Marcio Buss, Rodolfo Azevedo, Paulo Centoducatte, ...