Sciweavers

359 search results - page 70 / 72
» A section cache system designed for VLIW architectures
Sort
View
ICCAD
2008
IEEE
105views Hardware» more  ICCAD 2008»
14 years 5 months ago
Parameterized transient thermal behavioral modeling for chip multiprocessors
In this paper, we propose a new architecture-level parameterized transient thermal behavioral modeling algorithm for emerging thermal related design and optimization problems for ...
Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Mur...
CF
2004
ACM
14 years 2 months ago
A first glance at Kilo-instruction based multiprocessors
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
Marco Galluzzi, Valentin Puente, Adrián Cri...
MICRO
2009
IEEE
168views Hardware» more  MICRO 2009»
14 years 3 months ago
Ordering decoupled metadata accesses in multiprocessors
Hardware support for dynamic analysis can minimize the performance overhead of useful applications such as security checks, debugging, and profiling. To eliminate implementation ...
Hari Kannan
ACSAC
2008
IEEE
14 years 3 months ago
Defending Against Attacks on Main Memory Persistence
Main memory contains transient information for all resident applications. However, if memory chip contents survives power-off, e.g., via freezing DRAM chips, sensitive data such a...
William Enck, Kevin R. B. Butler, Thomas Richardso...
SIGCOMM
2009
ACM
14 years 3 months ago
A programmable overlay router for service provider innovation
The threat of commoditization poses a real challenge for service providers. While the end-to-end principle is often paraphrased as “dumb network, smart end-systems”, the origi...
Bruce S. Davie, Jan Medved