Sciweavers

249 search results - page 14 / 50
» A secure scan design methodology
Sort
View
ASPDAC
2005
ACM
81views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Power estimation starategies for a low-power security processor
In this paper, we present the power estimation methodologies for the development of a low-power security processor that contains significant amount of logic and memory. For the lo...
Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling C...
ACSAC
2004
IEEE
13 years 11 months ago
CTCP: A Transparent Centralized TCP/IP Architecture for Network Security
Many network security problems can be solved in a centralized TCP (CTCP) architecture, in which an organization's edge router transparently proxies every TCP connection betwe...
Fu-Hau Hsu, Tzi-cker Chiueh
DAC
2003
ACM
14 years 27 days ago
Test application time and volume compression through seed overlapping
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architect...
Wenjing Rao, Ismet Bayraktaroglu, Alex Orailoglu
ISJGP
2010
13 years 4 months ago
On the Hardware Implementation Cost of Crypto-Processors Architectures
A variety of modern technologies such as networks, Internet, and electronic services demand private and secure communications for a great number of everyday transactions. Security ...
Nicolas Sklavos
ASE
2008
120views more  ASE 2008»
13 years 7 months ago
Requirements model generation to support requirements elicitation: the Secure Tropos experience
In the last years several efforts have been devoted by researchers in the Requirements Engineering community to the development of methodologies for supporting designers during req...
Nadzeya Kiyavitskaya, Nicola Zannone