—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
An architecture is proposed for the realization of real-time edge-extraction filtering operation in an Address-Event-Representation (AER) vision system. Furthermore, the approach ...
Teresa Serrano-Gotarredona, Andreas G. Andreou, Be...
Service-centric systems are driven more and more towards self-adaptation in order to satisfy QoS in highly dynamic environments. However, the young age and immaturity of this doma...
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
Andrea Pellegrini, Joseph L. Greathouse, Valeria B...