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ASPDAC
1999
ACM
93views Hardware» more  ASPDAC 1999»
13 years 12 months ago
Optimization of Linear Placements for Wirelength Minimization with Free Sites
We study a type of linear placement problem arising in detailed placement optimization of a given cell row in the presence of white-space (extra sites). In this single-row placeme...
Andrew B. Kahng, Paul Tucker, Alexander Zelikovsky
DAC
2005
ACM
13 years 9 months ago
Faster and better global placement by a new transportation algorithm
We present BonnPlace, a new VLSI placement algorithm that combines the advantages of analytical and partitioning-based placers. Based on (non-disjoint) placements minimizing the t...
Ulrich Brenner, Markus Struzyna
DATE
2008
IEEE
104views Hardware» more  DATE 2008»
14 years 2 months ago
A Novel Approach for EMI Design of Power Electronics
The placement of passive components significantly influences the EMI behavior of power electronic systems. Particularly filter components are affected by magnetic field coupling r...
Bernd Stube, Bernd Schröder, Eckart Hoene, An...
ISPD
2005
ACM
168views Hardware» more  ISPD 2005»
14 years 1 months ago
Capo: robust and scalable open-source min-cut floorplacer
In this invited note we describe Capo, an open-source software tool for cell placement, mixed-size placement and floorplanning with emphasis on routability. Capo is among the fas...
Jarrod A. Roy, David A. Papa, Saurabh N. Adya, Hay...
TCAD
2008
114views more  TCAD 2008»
13 years 7 months ago
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...
David A. Papa, Tao Luo, Michael D. Moffitt, Chin-N...