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» A statistical multiprocessor cache model
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ICCAD
2008
IEEE
105views Hardware» more  ICCAD 2008»
14 years 6 months ago
Parameterized transient thermal behavioral modeling for chip multiprocessors
In this paper, we propose a new architecture-level parameterized transient thermal behavioral modeling algorithm for emerging thermal related design and optimization problems for ...
Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Mur...
HPCA
2009
IEEE
14 years 10 months ago
A first-order fine-grained multithreaded throughput model
Analytical modeling is an alternative to detailed performance simulation with the potential to shorten the development cycle and provide additional insights. This paper proposes a...
Xi E. Chen, Tor M. Aamodt
ISCA
1993
IEEE
153views Hardware» more  ISCA 1993»
14 years 1 months ago
An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
Per Stenström, Mats Brorsson, Lars Sandberg
ISORC
2009
IEEE
14 years 4 months ago
Thread-Local Scope Caching for Real-time Java
There is increasing convergence between the fields of parallel and embedded computing. The demand for more functionality in embedded devices means that complex multicore architec...
Andy J. Wellings, Martin Schoeberl
SIGOPS
2010
179views more  SIGOPS 2010»
13 years 4 months ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...