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» A statistical multiprocessor cache model
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INFOCOM
2003
IEEE
14 years 19 days ago
Asymptotic Insensitivity of Least-Recently-Used Caching to Statistical Dependency
Abstract— We investigate a widely popular Least-RecentlyUsed (LRU) cache replacement algorithm with semi-Markov modulated requests. Semi-Markov processes provide the flexibility...
Predrag R. Jelenkovic, Ana Radovanovic
IEEEPACT
2008
IEEE
14 years 1 months ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang
ISCA
1993
IEEE
157views Hardware» more  ISCA 1993»
13 years 11 months ago
The Performance of Cache-Coherent Ring-based Multiprocessors
Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective u...
Luiz André Barroso, Michel Dubois
CODES
2007
IEEE
14 years 1 months ago
Event-based re-training of statistical contention models for heterogeneous multiprocessors
Embedded single-chip heterogeneous multiprocessor (SCHM) systems experience frequent system events such as task preemption, power-saving voltage/frequency scaling, or arrival of n...
Alex Bobrek, JoAnn M. Paul, Donald E. Thomas
SC
1992
ACM
13 years 11 months ago
Willow: A Scalable Shared Memory Multiprocessor
We are currently developing Willow, a shared-memory multiprocessor whose design provides system capacity and performance capable of supporting over a thousand commercial microproc...
John K. Bennett, Sandhya Dwarkadas, Jay A. Greenwo...