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DSD
2003
IEEE
121views Hardware» more  DSD 2003»
14 years 3 months ago
CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors
With shrinking feature size of silicon fabrication technology, architects are putting more and more logic into a single die. While one might opt to use these transistors for build...
Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemi...
DSN
2002
IEEE
14 years 3 months ago
Time-Constrained Failure Diagnosis in Distributed Embedded Systems
—Advanced automotive control applications such as steer-by-wire are typically implemented as distributed systems comprising many embedded processors, sensors, and actuators inter...
Nagarajan Kandasamy, John P. Hayes, Brian T. Murra...
ICPP
1999
IEEE
14 years 2 months ago
Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures
Loops are the main time consuming part of programs based on floating point computations. The performance of the loops is limited either by recurrences in the computation or by the...
David López, Josep Llosa, Eduard Ayguad&eac...
IEEEPACT
2006
IEEE
14 years 4 months ago
Core architecture optimization for heterogeneous chip multiprocessors
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi
CLUSTER
2005
IEEE
14 years 3 months ago
A Feasibility Analysis of Power Awareness in Commodity-Based High-Performance Clusters
We present a feasibility study of a power-reduction scheme that reduces the thermal power of processors by lowering frequency and voltage in the context of high-performance comput...
Chung-Hsing Hsu, Wu-chun Feng