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DSD
2003
IEEE

CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors

14 years 5 months ago
CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors
With shrinking feature size of silicon fabrication technology, architects are putting more and more logic into a single die. While one might opt to use these transistors for building complex single processor based architectures, recent trends indicate a shift towards onchip multiprocessor systems since they are simpler to implement and can provide better performance. An important problem in on-chip multiprocessors is energy consumption. In particular, on-chip cache structures can be major energy consumers. In this work, we study energy behavior of different cache architectures, and propose a new architecture, where processors share a single, banked cache using crossbar interconnects. Our detailed cycle-accurate simulations show that this cache architecture brings energy benefits ranging from 9% to 26% (over an architecture where each processor has a private cache).
Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemi
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where DSD
Authors Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Ismail Kadayif
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