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» A study of slipstream processors
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PLDI
1995
ACM
14 years 1 months ago
Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
Jack L. Lo, Susan J. Eggers
DATE
2010
IEEE
147views Hardware» more  DATE 2010»
14 years 21 days ago
Detecting/preventing information leakage on the memory bus due to malicious hardware
An increasing concern amongst designers and integrators of military and defense-related systems is the underlying security of the individual microprocessor components that make up ...
Abhishek Das, Gokhan Memik, Joseph Zambreno, Alok ...
AAAI
2010
13 years 11 months ago
Evolving Compiler Heuristics to Manage Communication and Contention
As computer architectures become increasingly complex, hand-tuning compiler heuristics becomes increasingly tedious and time consuming for compiler developers. This paper presents...
Matthew E. Taylor, Katherine E. Coons, Behnam Roba...
DAGSTUHL
2008
13 years 11 months ago
Uniprocessor EDF Feasibility is an Integer Problem
The research on real-time scheduling has mostly focused on the development of algorithms that allows to test whether the constraints imposed on the task execution (often expressed ...
Enrico Bini
IJCAI
2003
13 years 11 months ago
Contract Algorithms and Robots on Rays: Unifying Two Scheduling Problems
We study two apparently different, but formally similar, scheduling problems. The first problem involves contract algorithms, which can trade off run time for solution quality, a...
Daniel S. Bernstein, Lev Finkelstein, Shlomo Zilbe...