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» A study of slipstream processors
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ANCS
2006
ACM
13 years 11 months ago
Efficient memory utilization on network processors for deep packet inspection
Deep Packet Inspection (DPI) refers to examining both packet header and payload to look for predefined patterns, which is essential for network security, intrusion detection and c...
Piti Piyachon, Yan Luo
CASES
2001
ACM
13 years 11 months ago
Transparent data-memory organizations for digital signal processors
Today's digital signal processors (DSPs), unlike general-purpose processors, use a non-uniform addressing model in which the primary components of the memory system--the DRAM...
Sadagopan Srinivasan, Vinodh Cuppu, Bruce L. Jacob
ISCA
1995
IEEE
92views Hardware» more  ISCA 1995»
13 years 11 months ago
A Comparison of Full and Partial Predicated Execution Support for ILP Processors
One can e ectively utilize predicated execution to improve branch handling in instruction-level parallel processors. Although the potential bene ts of predicated execution are hig...
Scott A. Mahlke, Richard E. Hank, James E. McCormi...
ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
13 years 11 months ago
High-Bandwidth Address Translation for Multiple-Issue Processors
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
Todd M. Austin, Gurindar S. Sohi
JCP
2007
154views more  JCP 2007»
13 years 7 months ago
Partially Reconfigurable Vector Processor for Embedded Applications
—Embedded systems normally involve a combination of hardware and software resources designed to perform dedicated tasks. Such systems have widely crept into industrial control, a...
Muhammad Z. Hasan, Sotirios G. Ziavras