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DATE
2010
IEEE
157views Hardware» more  DATE 2010»
14 years 18 days ago
RMOT: Recursion in model order for task execution time estimation in a software pipeline
Abstract—This paper addresses the problem of execution time estimation for tasks in a software pipeline independent of the application structure or the underlying architecture. A...
Nabeel Iqbal, M. A. Siddique, Jörg Henkel
FPL
2009
Springer
117views Hardware» more  FPL 2009»
14 years 4 days ago
Data parallel FPGA workloads: Software versus hardware
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) ...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
MICRO
1999
IEEE
105views Hardware» more  MICRO 1999»
13 years 11 months ago
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
Todd M. Austin
AUSAI
2006
Springer
13 years 11 months ago
Robust Character Recognition Using a Hierarchical Bayesian Network
There is increasing evidence to suggest that the neocortex of the mammalian brain does not consist of a collection of specialised and dedicated cortical architectures, but instead ...
John Thornton, Torbjorn Gustafsson, Michael Blumen...
NGC
2000
Springer
13 years 11 months ago
The use of hop-limits to provide survivable ATM group communications
We examine the use of a hop-limit constraint with techniques to provide survivability for connection-oriented ATM group communications. A hop-limit constraint is an approach that ...
William Yurcik, David Tipper, Deep Medhi
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