Abstract—This paper addresses the problem of execution time estimation for tasks in a software pipeline independent of the application structure or the underlying architecture. A...
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) ...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
There is increasing evidence to suggest that the neocortex of the mammalian brain does not consist of a collection of specialised and dedicated cortical architectures, but instead ...
John Thornton, Torbjorn Gustafsson, Michael Blumen...
We examine the use of a hop-limit constraint with techniques to provide survivability for connection-oriented ATM group communications. A hop-limit constraint is an approach that ...