214 search results - page 14 / 43 » A system level design methodology for the optimization of he... |
TSE
2002
13 years 7 months ago
2002
The complexity of hardware/software codesign of embedded real-time signal processing systems can be reduced by rapid system prototyping (RSP). However, existing RSP frameworks do n...
ISVLSI
2002
IEEE
14 years 17 days ago
2002
IEEE
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper presents a design methodology for fully reconfigurable low-voltage Delta-Sigma converters as for instance used in next-generation wireless applications. The design metho...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
- In this paper, we present a design methodology for automatic platform generation of future heterogeneous systems where communication happens via the Network-onChip (NoC) approach...
IEEEPACT
2009
IEEE
13 years 5 months ago
2009
IEEE
Efficiently using the hardware capabilities of the Cell processor, a heterogeneous chip multiprocessor that uses several levels of parallelism to deliver high performance, and bei...