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HPCA
2009
IEEE
14 years 9 months ago
Adaptive Spill-Receive for robust high-performance caching in CMPs
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
Moinuddin K. Qureshi
ISCA
2007
IEEE
149views Hardware» more  ISCA 2007»
14 years 2 months ago
Virtual private caches
Virtual Private Machines (VPM) provide a framework for Quality of Service (QoS) in CMP-based computer systems. VPMs incorporate microarchitecture mechanisms that allow shares of h...
Kyle J. Nesbit, James Laudon, James E. Smith
CLOUD
2010
ACM
14 years 1 months ago
Stateful bulk processing for incremental analytics
This work addresses the need for stateful dataflow programs that can rapidly sift through huge, evolving data sets. These data-intensive applications perform complex multi-step c...
Dionysios Logothetis, Christopher Olston, Benjamin...
IPPS
2008
IEEE
14 years 3 months ago
High-speed string searching against large dictionaries on the Cell/B.E. Processor
Our digital universe is growing, creating exploding amounts of data which need to be searched, protected and filtered. String searching is at the core of the tools we use to curb...
Daniele Paolo Scarpazza, Oreste Villa, Fabrizio Pe...
DAC
2009
ACM
14 years 9 months ago
Contract-based system-level composition of analog circuits
Efficient system-level design is increasingly relying on hierarchical design-space exploration, as well as compositional methods, to shorten time-to-market, leverage design re-use...
Xuening Sun, Pierluigi Nuzzo, Chang-Ching Wu, Albe...