118 search results - page 12 / 24 » A technique for minimizing power during FPGA placement |
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
Process variations due to lens aberrations are to a large extent systematic, and can be modeled for purposes of analyses and optimizations in the design phase. Traditionally, vari...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
- Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult pro...
FPGA
2009
ACM
14 years 3 months ago
2009
ACM
Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the inte...
ECRTS
2010
IEEE
13 years 9 months ago
2010
IEEE
Energy conservation is an important issue in the design of embedded systems. Dynamic Voltage Scaling (DVS) and Dynamic Power Management (DPM) are two widely used techniques for sav...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...