118 search results - page 14 / 24 » A technique for minimizing power during FPGA placement |
FPGA
2009
ACM
14 years 3 months ago
2009
ACM
Reconfigurable high-performance computing systems (RHPC) have been attracting more and more attention over the past few years. RHPC systems are a promising solution for accelerati...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
DAC
2009
ACM
14 years 9 months ago
2009
ACM
Elevated chip temperatures are true limiters to the scalability of computing systems. Excessive runtime thermal variations compromise the performance and reliability of integrated...
DFT
2005
IEEE
13 years 10 months ago
2005
IEEE
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
TSP
2008
13 years 8 months ago
2008
The focus of this paper is on VLIW instruction scheduling that minimizes the variation of power consumed by the processor during the execution of a target program. We use rough set...