118 search results - page 15 / 24 » A technique for minimizing power during FPGA placement |
DAC
1995
ACM
14 years 2 hour ago
1995
ACM
This paper describes a technique for calculating the switching activity of a set of registers shared by di erent data values. Based on the assumption that the joint pdf (probabili...
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
With the shrinking of transistors continuing to follow Moore's Law and the non-scalability of conventional outof-order processors, multi-core systems are becoming the design ...
LCTRTS
2007
Springer
14 years 2 months ago
2007
Springer
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
- The current energy and environmental cost trends of datacenters are unsustainable. It is critically important to develop datacenter-wide power and thermal management (PTM) soluti...
ISQED
2006
IEEE
14 years 2 months ago
2006
IEEE
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...