118 search results - page 8 / 24 » A technique for minimizing power during FPGA placement |
VTS
2000
IEEE
13 years 11 months ago
2000
IEEE
Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause prob...
TVLSI
1998
13 years 7 months ago
1998
Abstract— The growing popularity of look-up table (LUT)based field programmable gate arrays (FPGA’s) has renewed the interest in functional or Roth–Karp decomposition techni...
ERSA
2006
13 years 8 months ago
2006
Thermal monitoring of a design plays a vital role to ensure safe and reliable thermal operating conditions. Thermal monitoring by employing thermal sensors is a popular technique ...
CGO
2005
IEEE
14 years 1 months ago
2005
IEEE
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
SAC
2005
ACM
14 years 28 days ago
2005
ACM
This paper presents an efficient technique for placement and routing of sensors/actuators and processing units in a grid network. Our system requires an extremely high level of ro...