563 search results - page 13 / 113 » A theory-based alternative for the design of instruction: fu... |
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function ca...
IFIP
1993
Springer
13 years 11 months ago
1993
Springer
An advanced Self-Timed Reduced Instruction Set Computer (ST-RISC) architecture is described. It is designed hierarchically, and is formally specified functionally at the various ...
MICRO
2002
IEEE
14 years 19 days ago
2002
IEEE
Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consum...
SIGSOFT
2004
ACM
14 years 8 months ago
2004
ACM
Exploring alternative options is at the heart of the requirements and design processes. Different alternatives contribute to different degrees of achievement of non-functional goa...
DATE
2002
IEEE
14 years 20 days ago
2002
IEEE
This paper describes the AccuPower toolset -- a set of simulation tools accurately estimating the power dissipation within a superscalar microprocessor. AccuPower uses a true hard...