This paper proposes a cycle accounting architecture for Simultaneous Multithreading (SMT) processors that estimates the execution times for each of the threads had they been execu...
Many real-time systems must control their CPU utilizations in order to meet end-to-end deadlines and prevent overload. Utilization control is particularly challenging in distribut...
Xiaorui Wang, Dong Jia, Chenyang Lu, Xenofon D. Ko...
The control flow of common processors does not match the specific needs of reactive systems. Key issues for these systems are preemption and concurrency, combined with timing pred...
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...
We consider the determinism checking of XML Schema content models, as required by the W3C Recommendation. We argue that currently applied solutions have flaws and make processors...