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MICRO
1999
IEEE
98views Hardware» more  MICRO 1999»
14 years 2 months ago
Access Region Locality for High-Bandwidth Processor Memory System Design
This paper studies an interesting yet less explored behavior of memory access instructions, called access region locality. Unlike the traditional temporal and spatial data localit...
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
HIPC
2005
Springer
14 years 3 months ago
Application of Reduce Order Modeling to Time Parallelization
We recently proposed a new approach to parallelization, by decomposing the time domain, instead of the conventional space domain. This improves latency tolerance, and we demonstrat...
Ashok Srinivasan, Yanan Yu, Namas Chandra
PPOPP
2006
ACM
14 years 3 months ago
Minimizing execution time in MPI programs on an energy-constrained, power-scalable cluster
Recently, the high-performance computing community has realized that power is a performance-limiting factor. One reason for this is that supercomputing centers have limited power ...
Robert Springer, David K. Lowenthal, Barry Rountre...
ISCA
1998
IEEE
107views Hardware» more  ISCA 1998»
14 years 2 months ago
Memory Dependence Prediction Using Store Sets
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...
George Z. Chrysos, Joel S. Emer
HPDC
2002
IEEE
14 years 2 months ago
Using Kernel Couplings to Predict Parallel Application Performance
Performance models provide significant insight into the performance relationships between an application and the system used for execution. The major obstacle to developing perfor...
Valerie E. Taylor, Xingfu Wu, Jonathan Geisler, Ri...